A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process

Abstract A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the is a differential 9-stage ring oscillator, based on multi-path architecture. novel version this design proposed, along with an analytical model linearity. allowed us to understand source performance superiority (in terms linearity) our and predict further improvements. oscillator integrated event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For reason for compactness simplicity architecture, proposed TDC suitable applications which large number converters massive parallelization are required such as High-Energy Physics medical imaging detector systems. test chip has been fabricated tested. shows DNL≤1.3 LSB, INL≤2 single-shot precision 19.5 (0.58 LSB). dissipates power 5.4 mW overall.